For high-density wiring (for example, high density integrated circuit, interposer wiring, print wiring board, etc. The same below) to comply with DRAM standards such as DDR3 and DDR4, etc., it becomes necessary to have at least 10 ultrahigh-speed parallel bus signals of frequencies greater than 1 GHz. It becomes necessary for such ultrahigh-speed parallel bus signals to reach from the driver to the receiver with a wiring delay error within the range of 10 pico-seconds.
When performing the wiring designing using CAD for such high-density wiring, in order to unify the delay time of the parallel bus signals, it becomes necessary to arrange the wire lengths of the parallel bus signals.
On the other hand, with high-density integrated circuit within high-density wiring, the pin's physical location is not unified. Because of this, the wiring length of the parallel bus signal cannot be arranged by simply wiring from pin to pin. Therefore, in order to arrange each wiring length, the meander wiring, wiring which has a staggered form (serpentine shape), is used.
To arrange the wiring length of the parallel bus signal, it is necessary to measure the wiring length. For this reason, wiring length measurement becomes an extremely important design guideline. Because of this, CAD has the ability to calculate the wiring length of high-density wiring, which is the design target, and the ability to measure the wiring length with high precision is required.
Conventionally, after configuration of the multiple clock synchronous sequential circuit has been completed, the distance from the clock building device's clock output terminal to the clock input terminal of each clock synchronous sequential circuit is measured and the technology that performs the wiring to ensure that each distance is equal is disclosed (Patent literature 1 reference).